Deposited tunneling oxide

ABSTRACT

An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.

This is a division of application Ser. No. 07/545,122 now U.S. Pat. No.5,219,774, which issued Jun. 15, 1993 filed Jun. 26, 1990, which is acontinuation of Ser. No. 07/195,766 filed May 17, 1988, now abandoned.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuit processing andmore specifically to a method of depositing tunneling oxide in anelectrically erasable read-only memory device.

BACKGROUND OF THE INVENTION

EEPROM devices are nonvolatile memory devices in which the presence orabsence of charge on a floating gate electrode indicates a binary one orzero. One EEPROM device is described in U.S. Pat. No. 4,579,706,entitled “Nonvolatile Electrically Alterable Memory”. This patent isherein incorporated by reference. In this type of EEPROM device, thefloating gate electrode is electrically insulated from the otherelectrodes of the device by one or more layers of tunneling oxide.Electrical charge is transferred to the floating gate by placing avoltage on a programming electrode which is sufficient to causeelectrons to tunnel through the tunneling oxide to the floating gateelectrode. In EEPROM devices, the tunneling oxide can conduct only alimited amount of charge under the high fields imposed across the oxideduring tunneling before the tunneling oxide fails or breaks down, thuslimiting the number of programming cycles. In some tunneling elements inan EEPROM array, this failure may occur in less than approximately10,000 programming cycles, depending on the uniformity and intrinsicdefect density of the tunneling oxide layer or layers.

The characteristics of the tunneling oxide layer are critical to thelife and operation of an EEPROM device. In prior EEPROM devices,tunneling oxides are produced by growing an oxide using a thermaloxidation process. However, with this type of process, the oxide defectdensity is quite high, which causes a large number of early breakdownfailures. As presently understood, this is because any defects in theunderlying silicon may propagate into the silicon dioxide layer as it isgrown. Furthermore, during the thermal oxidation process, the tunnelingoxide develops a high level of stress. As presently understood, thisphenomena causes defects resulting in early or premature failures in theoxide during tunneling, thus further limiting the life of the device. Notechnique is known for thermally growing a low-stress tunneling oxide,while providing an oxide layer with substantially zero defects.

SUMMARY OF THE INVENTION

Briefly described, the present invention contemplates a method and meansof depositing a tunneling oxide layer between two conductors with a lowpressure, low temperature chemical vapor deposition (LPCVD) process.Preferably, tetraethylorthosilicate (TEOS) is used for this depositionprocess. Where the present method is used in an EEPROM device andpolysilicon layers are used for forming the device, the deposited oxideis formed as follows. According to the present invention, a first layerof polysilicon is deposited and patterned as desired. A layer of silicondioxide is then deposited by a decomposition of tetraethylorthosilicateto form a predetermined thickness of tunneling oxide on the surface ofthe polysilicon. The oxide layer formed from the depositedtetraethylorthosilicate is then thermally annealed and densified.Preferably, this is performed using a mixture of steam and an inert gas,such as argon, at a predetermined temperature. The process may berepeated where more than one tunneling layer is desired. Wherenecessary, prior to depositing the tetraethylorthosilicate, whereenhanced emission structures are desired on the surface of thepolysilicon, a layer of relatively thin oxide thermal oxide may be grownon the surface of the polysilicon.

Accordingly, it is an object of the present invention to provide atunneling oxide in an EEPROM device which may be deposited with a lowpressure chemical vapor deposition process.

It is another object of the present invention to improve the usefullifetime of an EEPROM device.

It is yet another object of the present invention to improve the yieldin EEPROM processing.

It is another object of the present invention to improve the reliabilityof an EEPROM device.

It is yet another object of the present invention to produce a tunnelingdielectric that is not limited by the underlying defect density of thematerial on which the oxide layer is being formed.

It is yet another object of the present invention to produce a tunnelingdielectric having minimum stress.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects will be apparent through the description belowand the accompanying drawings in which:

FIG. 1 is a cutaway view of a three layer thick-oxide EEPROM deviceconstructed in accordance with the present invention; and

FIG. 2 is a flow diagram detailing a process for manufacturing one ofthe tunneling oxide regions of the device of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is shown a cutaway view of a three layerpolysilicon device which may advantageously employ the tunneling oxidelayer of the present invention. The operation and manufacture of thedevice of FIG. 1 is substantially described in U.S. Pat. No. 4,599,706,the difference being the substitution of the present deposited oxide forthe thermal oxide described in the above U.S. patent.

The EEPROM device 10 of FIG. 1 is formed on a substrate 12 whichcomprises a “p”-type semiconductor material. Two n+ regions 20, 22 arediffused on opposing ends of the substrate. An n− region 24 is diffusedin a central upper region of substrate 12. The n+ source, drain regions20, 22 and n− diffusion 24 may be formed using a conventional well knowndiffusion process. The EEPROM device 10 further includes a polysiliconelectrode 24 which is isolated from substrate 12 by oxide region 30 andpolysilicon electrodes 26 and 28 which are separated from the substrate,and each other by tunneling oxide regions or elements 32 and 34. Inprior EEPROM devices, the oxide used for forming these tunnelingelements 32, 34 was thermally grown, which is believed to cause stressand defects in tunneling oxide elements 32, 34 because defects from theunderlying silicon substitution or polysilicon region may propagate intothe tunneling oxide.

The present invention contemplates the use of a low pressure chemicalvapor deposition process to form elements 32, 34. In a thermal oxidationprocess, once the tunneling oxides are grown, subsequent thermalprocessing causes thermal stress in the oxide, thus causing additionalbreakdown and charge trap-up problems in the device. The presentinvention contemplates the use of a low temperature process to minimizethermal oxide growth during the processing of the device, whichsignificantly reduces stress and thereby increases the useful life ofthe device. This feature has also been found to enhance electrontunneling in the resulting device. Furthermore, the low pressurechemical vapor deposition process used according to the presentinvention for forming an oxide layer is believed to avoid thepropagation of defects into the oxide from the underlying substrate orpolysilicon.

Atmospheric deposition of silicon has been attempted in the past usingsilicon rich SiO₂ in a chemical vapor deposition process. One suchprocess is described in an article entitled “Silicon—Rich SiO₂ andThermal SiO₂ Dual Dielectric for Yield Improvement and HighCapacitance”, IEEE Transactions on Electron Devices, Vol. ED-30, No. 8,P. 894, August 1983. The process described in this publication isexperimental and has been found to be inadequate for use inmanufacturing tunneling oxides because silicon rich SiO₂ is not astoichiometric compound and thus contains impurities which affect theuniformity of the deposited oxide. The use of an atmospheric depositionalso creates large variations in thickness of the resulting layer and,therefore, silicon rich SiO₂ has only been used for relatively thicklayers. Furthermore, although the added silicon in the above processprovides a form of enhancement for electron tunneling through thedielectric formed by this process, it's not as efficient as theformation of a textured surface on the underlying silicon substrate orpolysilicon conductive layer. This is because the silicon rich SiO₂apparently forms regions or balls of silicon in the silicon dioxide nearthe surface thereof but spread out. Thus, they are not conductive witheach other or with the surface of the dielectric and so are lessefficient as enhanced emission structures as compared with the texturedsurface of a polysilicon layer.

Other commonly used deposited oxide processes have been developed in thepast for forming oxide layers between metal layers in the range of 0.5microns to several microns or for filling trenches. However, theseprocesses have been found to be inadequate for forming thinner layers(on the order of 2000 or less Angstroms) such as are required fortunneling oxide elements, because these processes have poor uniformityand suffer from low breakdown voltages at such thicknesses. One suchprocess employs tetraethylorthosilicate (TEOS) which is available fromthe J.C. Schumacher Co. and has typically been used for thick oxideprocesses. This material is also called tetraethyloxysilane.

The present invention overcomes the above problem by modifying the knowndeposited oxide process using a densification or annealing step on theTEOS deposited oxide during processing. It has been found that byexposing the TEOS deposited oxide to a steam and inert gas mixture at arelatively high temperature, the properties of the TEOS oxide aremodified to equal or exceed those of thermally grown oxides. Theresulting material has substantially improved dielectric properties andthe resulting material is substantially free of leakage and does notbreak down in the presence of a strong electric field. It is believedthat this annealing process provides more uniform molecular bonding bypermitting greater viscous flow in the TEOS deposited oxide thusreducing or eliminating defects in the resulting dielectric layer. Sincethis steam ambient at the desired annealing temperature grows oxide at arelatively fast rate, which would thereby increase the thickness of thedielectric layer, the inert gas provides a partial pressure which isused to slow this undesired oxide growth rate while allowing theannealing process to proceed. The process of the present invention hasbeen found to increase the total charge conducted through the dielectriclayer by at least one order of magnitude before catastrophic breakdown,while at the same time providing a dramatic improvement in processingyields.

Referring now to FIGS. 2A and 2B, the process 200 begins with step 202wherein an initial layer of gate oxide, approximately 400 Angstromsthick is deposited on a substrate. This oxide layer may be formed with aconventional thermal oxide process. In step 204 the first layer ofpolysilicon is formed with a conventional polysilicon depositionprocess. The first layer of polysilicon is deposited approximately 4000Angstrons thick. In step 206, the first layer of polysilicon is doped torender the polysilicon layer conductive. The first layer of polysiliconmay then be masked in step 210 and etched in step 212 using either areactive ion etch or wet etch process. In the preferred practice of thepresent invention, it is desirable that the surface of each tunnelingregion be somewhat irregular to promote electron tunneling. Thesesurface irregularities or microtextured surfaces are formed by thermallyoxidizing the surface of the polysilicon layer with step 216. Thethermal oxide of step 216 is then etched back to leave a layer of oxideapproximately 150 Angstroms thick. The tunneling oxide layer is thenformed by steps 220, 222 and 223. In step 220, oxide is deposited overthe relatively thin layer of thermal oxide using a low pressure chemicalvapor deposition system with TEOS as the preferred gaseous medium. TheTEOS gas is supplied via a bubbler by direct pull with the furnacetemperature at approximately 600° C. The deposition rate is controlledprimarily by the bubbler and furnace temperatures. The oxide isdeposited to create an oxide layer of between 250 and 2000 Angstromsthick. This oxide layer is then annealed in steps 222 and 223.

The annealing process of step 222 is done by exposing the TEOS producedsilicon dioxide layer to a gaseous mixture of steam and argon at atemperature range of approximately 700-1100° C. for approximately 1-5minutes. This is preferrably followed by further thermal annealing in asolely nitrogen ambient at step 223 to prevent further oxidation of thesurface. This is performed at the same approximate temperature range forbetween 2 and 20 minutes. Other annealing processes, such as rapidoptical annealing may also be employed at different temperatures andtiming as is known in the art for thick deposited oxide layers. Theprocess is continued at step 224 wherein the next layer of polysilicon,approximately 4000-6000 Angstroms thick, is deposited by conventionalmeans. The second layer of polysilicon is then doped in step 226. Thesecond layer of polysilicon is then masked for further processing instep 230. Depending on whether additional layers of polysilicon arerequired, decision 223 either routes the process back to step 212 orexits the process at step 234. The resulting structure may then bemetalized and finished according to conventional means.

In summary, an improved method and means for making a tunneling oxideusing TEOS deposited silicon dioxide has been described. Accordingly,other uses and modifications will be apparent to a person of ordinaryskill in the art without departing from the scope of the presentinvention.

What is claimed is:
 1. An improved tunneling region for use with anintegrated circuit comprising: a first layer of polysilicon; a firstelectron tunneling layer of thermal oxide formed over said first layerof polysilicon; a second electron tunneling layer of annealed depositedsilicon dioxide formed over said first tunneling layer having athickness less than 2000 Angstroms thick, said silicon dioxide layerbeing formed by low pressure chemical vapor deposition comprising theuse of tetraethylorthosilicate; and a second layer of polysilicon formedover said layer of deposited silicon dioxide, such that when a biasvoltage is applied between said first layer of polysilicon and saidsecond layer of polysilicon, electron tunneling will occur from saidfirst layer of polysilicon to said second layer of polysilicon throughsaid first and second electron tunneling layers.
 2. The improvedtunneling region of claim 1 wherein said first tunneling layer ofthermal oxide forms a microtextured surface on top of said first layerof polysilicon for promoting electron tunneling.
 3. The improvedtunneling region of claim 1 wherein said first tunneling layer ofthermal oxide is approximately 150 Angstroms thick.
 4. A semiconductordevice including means for electron tunneling, comprising: a firstconductive layer; an annealed silicon dioxide tunneling layer having athickness less than 2000 Angstroms formed on top of said conductivelayer, said silicon dioxide layer being formed by low pressure chemicalvapor deposition comprising the use of tetraethylorthosilicate; a secondconductive layer formed on top of said silicon dioxide layer, said firstconductive layer acting as a source of tunneling electrons under anappropriate voltage bias condition, said second conductive layer servingas the receptor of said tunneling electrons.
 5. The device of claim 4further comprising a layer of thermal oxide between said firstconductive layer and said silicon dioxide tunneling layer for forming amicrotextured surface on said first conductive layer for promotingelectron tunneling therefrom.
 6. The device of claim 5 wherein saidthermally grown oxide layer is relatively thin in comparison to saidsilicon dioxide tunneling layer.
 7. The device of claim 5 wherein saidthermally grown oxide layer is approximately 150 Angstroms thick.
 8. Thedevice of claim 4 wherein said silicon dioxide layer is annealed insteam environment.
 9. The device of claim 4 wherein said firstconductive layer comprises polysilicon.
 10. The device of claim 9wherein said first conductive layer has a microtextured surface topromote electron tunneling.
 11. The device of claim 4 wherein saidsemiconductor device is part of an EEPROM.
 12. An improved tunnelingregion for use with an integrated circuit comprising: a first layer ofpolysilicon; a first electron tunneling layer of thermal oxide formedover said first layer of polysilicon; a second electron tunneling layerof annealed deposited silicon dioxide formed over said first tunnelinglayer having a thickness less than 2000 Angstroms thick, said silicondioxide layer being formed by low pressure chemical vapor deposition;and a second layer of polysilicon formed over said layer of depositedsilicon dioxide, such that when a bias voltage is applied between saidfirst layer of polysilicon and said second layer of polysilicon,electron tunneling will occur from said first layer of polysilicon tosaid second layer of polysilicon through said first and second electrontunneling layers.
 13. A semiconductor device including means forelectron tunneling, comprising: a first conductive layer; an annealedsilicon dioxide tunneling layer having a thickness less than 2000Angstroms formed on top of said conductive layer, said silicon dioxidelayer being formed by low pressure chemical vapor deposition; and asecond conductive layer formed on top of said silicon dioxide layer,said first conductive layer acting as a source of tunneling electronsunder an appropriate voltage bias condition, said second conductivelayer serving as the receptor of said tunneling electrons.